1. Field of the Invention
The present invention relates to multiplier circuitry for use in a data processing system. In particular, the present invention relates to a structure and method for using an arithmetic and logic unit (ALU) within a multiplier circuit.
2. Description of the Prior Art
FIG. 1a is a block diagram illustrating a conventional multiplier circuit 100 in the same data processing system as ALU 130. ALU 130 is a conventional circuit which performs arithmetic and logic operations within the data processing system. ALU 130 includes registers 131 and 132 which receive input data values from input nodes 102 and 103, respectively. These input data values typically include a plurality of parallel digital signals. The input data values stored in registers 131 and 132 are processed within ALU 130 in a manner known in the art such that a desired operation (e.g., addition) is performed on the two input data values. The resulting output signal from ALU 130 is provided to multiplexer 140 on bus 135.
Multiplier circuit 100 includes registers 111 and 112, carry save stage 110, pipeline register 116, carry propagate adder 118 and buses 104, 105, 115, 117 and 119. Multiplier circuit 100 receives a first data value from input node 102 on lead 104 and a second data value from input node 103 on bus 105. The first and second data values are typically read into registers 111 and 112, respectively. Carry save stage 110 receives the first and second data values from input registers 111 and 112 and in response produces a carry signal and a sum signal.
FIG. 1b is a schematic diagram of a conventional carry save stage 110 used in the multiplication of two 4-bit data values (e.g., A[3:0] and B[3:0]). AND gates 151-166 receive bits A0-A3 of A[3:0] and bits B0-B3 of B[3:0]. Carry save adders 170-185 are conventional circuits which are connected as illustrated.
FIG. 1c is a schematic diagram illustrating the operation of carry save adder 180. Carry save adders 170-179 and 181-185 operate in a manner similar to carry save adder 180. Carry save stage 110 (FIG. 1b) generates two output signals. One output signal is a sum signal S[6:0], which is made up of save bits S6-S0. The other output signal is a carry signal C[6:0], which includes carry bits C6-C1 as the six most significant bits and a zero bit as the least significant bit.
The carry and sum signals are provided to pipeline register 116 of carry propagate adder 118 on buses 115 and 117, respectively. Carry propagate adder 118 adds the sum and carry signals, thereby creating a third data value which is equal to the product of the first and second data values. This third data value is provided to multiplexer 140 on bus 119. When multiplier circuit 100 is enabled, a multiplexer select signal on bus 141 causes multiplexer 140 to route the third data value from multiplier circuit 100 through multiplexer 140 to output node 150 on bus 148.
During system operations which do not involve multiplier circuit 100, the first and second data values are provided from input nodes 102 and 103 to registers 131 and 132 of ALU 130 as previously described. ALU 130 then performs the desired operation to provide an output signal on bus 135. The multiplexer select signal on bus 141 is selected to route the output signal of ALU 130 through multiplexer 140 to output node 150 on bus 148.
Multiplier circuit 100, ALU 130 and multiplexer 140 are often fabricated on a semiconductor chip. Because it is desirable to reduce the layout area of circuits fabricated on semiconductor chips, it would be desirable to minimize the layout area of the circuitry used to perform the functions previously described in connection with FIG. 1.